Polychronous modeling, analysis, verification and simulation for timed software architectures
نویسندگان
چکیده
منابع مشابه
Polychronous modeling, analysis, verification and simulation for timed software architectures
High-level modeling languages and standards, such as Simulink, SysML, MARTE and AADL (Architecture Analysis & Design Language), are increasingly adopted in the design of embedded systems so that system-level analysis, verification and validation (V&V) and architecture exploration are carried out as early as possible. This paper presents our main contribution in this aim by considering embedded ...
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ژورنال
عنوان ژورنال: Journal of Systems Architecture
سال: 2013
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2013.08.004